1. Field of the Invention
The present invention is related to a design method of an integrated circuit, in particular, to a gate array technology for designing a gate array integrated circuit including a clock tree which distributes multi-phase clock signals.
2. Description of the Related Art
A gate array technology (or a masterslice technology), which is one of the semi-custom design methods, is often used to reduce a TAT (turn around time) of integrated circuit design. The gate array technology involves providing a base array slice embedded with base cells, placing cells of a desired integrated circuit (that is, allocating the cells described in the desired integrated circuit to the base cells), and routing interconnections between the cells.
One of the significant issues of a gate array technology is clock skew management. Japanese Open Laid Patent Application No. Jp-A-Heisei 6-188397 discloses a gate array technology for reducing a clock skew caused by a difference in clock line lengths. In the disclosed gate array technology, a core region is divided into a sequential circuit cell region and remaining primitive cell regions. All the sequential circuit cells, which include therein sequential circuits such as flipflops, are arranged in the sequential circuit cell region. This architecture effectively reduces clock line lengths, and thus improves the clock skew.
Recent gate array integrated circuits often requires multi-phase clock signals, whose phases are different from each other. However, the aforementioned gate array technology is not suited for designing an integrated circuit in which multi-phase clock signals are used.
The applicant of the present application discloses an improved clock tree structure in Japanese Patent Application No. 2001-259136. The disclosed clock tree structure facilitates the distribution of multi-phase clock signals. In addition, the disclosed clock tree achieves uniform loads and lengths of the clock lines, and thereby effectively reduces the clock skew.
Design of a clock tree distributing multi-phase clock signals, however, often requires considerable man-hours. Each multi-phase clock signal may be inputted to thousands of sequential circuits, and thus an increased number of the multi-phase clock signals considerably complicates the clock tree in structure. This undesirably increases a TAT of integrated circuit design.
A need exists to provide a method for helping design an integrated circuit including a clock tree which distributes multi-phase clock signals.